This paper presents a 32Gb/s per lane UCIe-compatible chiplet interconnect utilizing an active local silicon interposer (aLSI) integrated with edge-triggered transceivers (ETT). The design achieves high energy efficiency of 0.36pJ/bit, area bandwidth density of 12.35Tbps/mm² and reduces PHY depth to 850μm. The ETT minimizes power and area by enabling compact top-die TX/RX designs. Fabricated in 3nm CMOS, the system demonstrates superior performance and competitive efficiency. A fully functional 32Gb/s link with sufficient design margin at 0.75V has been demonstrated. Specifically, an aggregate eye width of 20.46ps (65% UI) and an eye height of 530 mV across 64 lanes has been achieved in the KGP tests.

Wei-Chih Chen is with the Advanced Connectivity Dept., TSMC, Hsinchu, Taiwan, focusing on ultra-high-speed SerDes transceivers and chiplet heterogeneous integration. He has contributed significantly to PHY standards, particularly in the areas of link jitter, clocking, equalization, and channel modeling. He has published in top IEEE venues, including ISSCC, JSSC, VLSI, and CICC, and holds multiple TSMC patents. His research interests include ultra-high-speed wireline interfaces and high-throughput D2D interconnects.

This presentation introduces Verdi Agentic Debug, an AI-driven approach that transforms traditional RTL debug workflows into autonomous, intelligent processes. By tightly integrating large language models with Synopsys Verdi’s rich debug data (such as waveforms, logs, RTL, and assertions), the solution overcomes limitations of standalone LLMs to deliver accurate, context-aware root-cause analysis. This system enables engineers to automate complex debug tasks, significantly reducing manual effort and achieving up to 83% debug time savings. Ultimately, the approach drives a shift from interactive debugging to scalable, explainable, and autonomous debug workflows for SoC verification.

Allen Hsieh, PE manager of Verdi product team in TPG, Synopsys. Allen has more than 15 years of debugging and verification experience, now Allen is focusing on AI-driven debug flow and driving Verdi engagements in Synopsys.

AI technology is profoundly transforming digital interaction, yet deploying these complex models on edge devices like smartphones faces severe constraints in area, power, and bandwidth. This speech will delve into the real-world industry pain points of edge AI, particularly the "memory wall" and "power wall" erected by SRAM scaling bottlenecks and energy-intensive DRAM accesses. To break through these physical limits, MediaTek proposes a "Full-Stack Hardware-Software Co-Optimization" paradigm. We will share key technological breakthroughs presented at ISSCC over three consecutive years: from circuit-level weight-reload-free DCIM (NVE) and architecture-level line-based depth-first scheduling (MAE), to system-level hardware-software memory optimization (MADiC). We will demonstrate how these innovations maximize PPA efficiency and successfully empower top-tier AI imaging experiences in modern flagship smartphones.

Ming-En David Shih (M.S., National Chiao-Tung University, 2011) is a Deputy Director at MediaTek, leading the AI and Computer Vision IC design team for advanced multimedia applications. With extensive experience in mass-producing chips, his picture quality (PQ) systems currently power over one billion smartphones and TVs globally. Bridging academic research and real-world impact, his team has published three ISSCC papers in the past three years. Notably, his first-authored paper on a 3nm DCIM-based Neural Visual-Enhancement Engine (NVE) won the Anantha P. Chandrakasan Distinguished Technical Paper Award, the highest honor at ISSCC 2024. He is a two-time recipient of the MediaTek Innovation Award (ISCA, 2021 & 2025), the company's highest R&D honor. His current research focuses on real-time video processing and edge AI accelerators.