Poster Sessions | The 37th VLSI Design/CAD Symposium 第37屆超大型積體電路設計暨計算機輔助設計技術研討會

Poster 1

8月5日 (三) 13:30–15:00 鳳凰廳, 1F

場次主席

張亞寧, 國立成功大學

發表編號	類別	論文標題 / 作者 / 所屬學校/公司
P1-1	Analog & RF	A High-Linearity 5×5 Micro-LED Driver with Internally Compensated Active R-2R DAC for Optoelectronic Integration Chi-Lung Lo, Cai-Jun Hong, and Guo-Dung Su National Taiwan University
P1-2	Analog & RF	The Applications of FIR Quasi-Digital Current Control Technique on the 0.18μm Pseudo-LDO Regulator with Higher Efficiency, Fast Transient Response, and Extremely Absolutely-Stability on EMI Effects Jiann-Long Wu^1,2, Yuh-Shyan Hwang¹, and Huai-Kuei Wu² ¹National Taipei University of Technology ²Asia Eastern University of Science and Technology
P1-3	Analog & RF	A Low-Power Floating-Gate Reconfigurable OTA-C Filter with Near-ZTC Temperature Compensation Kai-Fong Chen¹, Hong-Yu Shih², Chun-Yen Huang¹, Huai-Jiun Chin², Yun-Ming Hsu², and Sheng-Yu Peng¹ ¹National Yang Ming Chiao Tung University ²National Taiwan University of Science and Technology
P1-4	Analog & RF	An Ultra-Low-Power RC Relaxation Oscillator with a Dual-mode Comparator Tun-Hsien Chien, Yu-Min Han, Yu-Tzu Liu, Tai-Hong Chen, and Tsung-Hsien Lin National Taiwan University
P1-5	Analog & RF	A Low-voltage Crystal-less Clock Generator Chin-Wei Hsu, Wen-Dong Ke, and Jen-Chieh Liu National United University
P1-6	Analog & RF	A 1.4-mW 12.8-GHz Fast-Locking Quadrature Phase-Locked Loop With a Mismatch-Suppressed Charge Pump for High-Speed Serial Links in 16-nm FinFET Yu-Wei Tu¹, Cong-Yu Huang¹, Zhao-Zhong Ho¹, Huan-Yi Chao¹, Xue-Yi Sun¹, E-Ray Hsieh², and Kuo-Hsing Cheng¹ ¹National Central University ²National Yang Ming Chiao Tung University
P1-7	Analog & RF	Magnetic Sensing System with Automatic Ripple Reduction and Variable Gain Readout Circuit Guo-Ming Sung, Guan-Zhe Huang, Sheng-Pin Tung, and Chih-Ping Yu National Taipei University of Technology
P1-8	Analog & RF	A Threshold-Aware Time-Domain Capacitance-to-Digital Sensing System for Point-of-Care Detection of Cardiovascular Biomarkers I-Hua Lee¹, Sasi Kiran Boilla⁴, Gwo-Bin Lee^3,4, and Tsung-Heng Tsai² ¹National Yang Ming Chiao Tung University ²National Yang Ming Chiao Tung University ³National Tsing Hua University ⁴National Tsing Hua University
P1-9	Analog & RF	An FPGA-Based Hardware Acceleration Platform Design for Long-Read Sequence Alignment Ching-Hsuan Tai, Po-Ju Shih, and Yi-Chang Lu National Taiwan University
P1-10	Analog & RF	A Compact Biomedical Readout System Integrating Potentiometric and Amperometric Measurements Yi-Wei Wu, Po-Hui Yang, Jung-Chuan Chou, Chih-Hsien Lai, Po-Yu Kuo, Yu-Hsun Nien, Jun-Zhu Jiang, and Hong-Wei Zhu National Yunlin University of Science and Technology
P1-11	Analog & RF	A 20 μW 18 nV/√𝐇𝐳 Noise Density Two-Stage CMOS Operational Transconductance Amplifier for Biomedical Monitoring Applications Kuei-Hao Huang, Po-Chen Cheng, Tian-Lin Zhang, Po-Yuan Chen, and Hong-Yeh Chang National Central University
P1-12	Analog & RF	A Dynamic Comparator-based PUF with Low Energy in 16-nm FinFET and 90-nm CMOS Jia-Sheng Lin and Hsiao-Chin Chen National Taiwan University of Science and Technology
P1-13	Analog & RF	Design of A 12-bit Successive-Approximation Register Analog-to-Digital Converter with Digital Error Correction Bo-Yu Cheng, Zong-Min Yang, and Po-Yu Kuo National Yunlin University of Science & Technology
P1-14	Analog & RF	Design of a 10-bit SAR ADC for Biomedical Applications Using a Reduced-Kickback Comparator and a Matching-Enhanced CDAC Layout Yi Feng and Chia-Ling Wei National Cheng Kung University
P1-15	Analog & RF	A 10-bit 10-GS/s 2x-TI DAC in 40-nm CMOS Chin-I LIN, Chi Tai Wang, and Yung-Hui Chung National Taiwan University of Science and Technology
P1-16	Analog & RF	A 12-bit 12-MS/s FCPC-Assisted CR-SAR ADC with Fixed-Point Capacitor-Mismatch Calibration Yu-Hsien Li¹, Shuenn-Yuh Lee¹, Wei-Song Wang², and Guan-Ying Huang² ¹National Cheng-Kung University ²Novatek Microelectronics Corp
P1-17	Analog & RF	Design of a Low-Power Discrete-Time CIFB 2-1 Sigma-Delta MASH ADC with Digital Error Cancellation in 16-nm FinFET Technology Yung-Hsuan Chen, Yue-Ze Lin, Yu-Sheng Chang, and Chien-Hsueh Chiang National Yunlin University of Science and Technology
P1-18	Analog & RF	A Third-Order Hybrid Error-Feedback Noise-Shaping SAR ADC Using Unity-Gain Buffer for Residue Transfer and In-Band Zero Placement Tzu-Chi Huang, Hao-Cheng Hsu, and Chien-Hung Kuo National Taiwan Normal University
P1-19	Analog & RF	A Partially Time-Interleaving Pipelined Noise-shaping SAR ADC with Amplifier Gain Error Shaping Chih-Fa Chung and Soon-Jyh Chang National Cheng Kung University
P1-20	Analog & RF	A 78.7-dB-SNDR Discrete-Time Hybrid ADC Employing Flash-Assisted Incremental Delta-Sigma Modulation and Ring Amplifiers Cheng-Han Lin, Hsin-Liang Chen, Jen-Shiun Chiang, and Chien-Huang Wu Tamkang University
P1-21	Digital & System	Design and Implementation of a Programmable Maritime Satellite Digital Baseband Receiver Chien-Chang Huang, Sheng-Yao Peng, Cheng-Yuan Liew, Cheng-Yan Xie, Ting-Sheng Lin, Yu-Lun Huang, Bo-Jun Chen, and Chung-An Shen National Taiwan University of Science and Technology
P1-22	Digital & System	The Algorithm and Hardware Architecture Design for Canonical Polyadic Decomposition of Ill Conditioned Tensors Liang-Yu Li, Wei-Nong Li, and Chung-An Shen National Taiwan University of Science and Technology
P1-23	Digital & System	The Algorithm and VLSI Architecture Design of Low Complexity Tensor Ring Decomposition Pei-Ting Lee, Ai-Yun Tseng, and Chung-An Shen National Taiwan University of Science and Technology
P1-24	Digital & System	The Impact of Misrouting Hardware Trojans on Eavesdropping Attacks in Network-on-Chip Chien-Wei Cheng and Kun-Chih Chen National Yang Ming Chiao Tung University
P1-25	Digital & System	Holistic Circuit-Layout Co-Design of a 0.4-V Area-Efficient Clocked Storage Element with Enhanced OD Regularity in 16nm FinFET Yao-Hsuan Ku, You-Wei Lin, Zhe-Kai Zhang, Wei-Je Huang, and Jin-Fa Lin Chaoyang University of Technology
P1-26	Digital & System	Eco-Secure-Net: A Communication-Efficient BNN-based Federated IDS for IoT Edge Devices with ASIC Implementation Ching-Ting Chiu National Taiwan Normal University
P1-27	Digital & System	FPGA Implementation of a Text-to-Image Network Based on GAN Architecture Liang-Xu Zhang and Szu-Hong Wang National Yunlin University of Science and Technology
P1-28	Digital & System	An FPGA-based UAV System Design for Real-Time River Pollution Monitoring Yu-Hua Hsu, Shu-Ting Huang, and Chun-Hsian Huang National Changhua University of Education
P1-29	Digital & System	Low-Power Matrix Computation Accelerator Based on Distributed Arithmetic Multiplication Architecture Chih-Kai Yang, Hung-Chen Su, Yi-An Chiu, and Chun-Chi Chen National Chiayi University
P1-30	Digital & System	Securing Medical Edge Accelerators Against On-Chip SRAM Faults via Ultra-Lightweight Spatial Redundancy Hsin Teng¹, Cheng-Hung Lin², and Jia-Kang Wang^1,3 ¹Yuan Ze University ²National Taiwan Normal University ³Far Eastern Memorial Hospital
P1-31	Digital & System	Sparsity-Aware CNN Accelerator Co-Design Yong-En Hong, Chih-I Lin, You-Shiuan Lin, and Chun-Lung Hsu National Central University
P1-32	Digital & System	APC–FPGA Heterogeneous AI System for Multi-Model Table Tennis Officiating Ji-Xiu Lu, Hsin-Te Hsu, Deng-Kai Yang, Yen-Ting Chu, and Chun-Lung Hsu National Central University
P1-33	Digital & System	HART: Hardware-Aligned Robust Training for Resource-Constrained Edge Device Chao-Wei Chang¹, Ya-Chi Peng¹, Yun-Hao Yang¹, Wan-Jung Chen¹, An-Yeu (Andy) Wu¹, Shih-Hsu Huang², and Mladen Berekovic³ ¹National Taiwan University ²Chung Yuan Christian University ³University of Lübeck
P1-34	Digital & System	A 2.21-W Parameter-Efficient CNN Hybrid Accelerator with Chebyshev-KAN Classifier on FPGA Hung-Yu Chen¹, Zhong-Long You¹, Tsung-Kai Weng², Chieh-Hsin Yu², Wen-Ling Ding², Chun-Lung Hsu², and E-Ray Hsieh² ¹National Central University ²National Yang Ming Chiao Tung University
P1-35	Digital & System	HLS-based R2D2 Accelerator for Keypoint Detection and Local Feature Description Chen-Xuan Huang and Tsung-Han Tsai National Central University
P1-36	Digital & System	Hardware Architecture Design and Implementation of a Transformer for the LoFTR Feature Matching Model Chih-hao Chang, Ting-Wei Lai, and Shiann-Rong Kuang National Sun Yat-sen University
P1-37	Digital & System	DPU-GAN: Deploying Text-to-Image GANs on FPGA Edge Platforms via DPU-Aligned Architecture Yu-Chan Sun and Shanq-Jang Ruan National Taiwan University of Science and Technology
P1-38	Digital & System	A Low-Power 1-D CNN Accelerator in 40-nm CMOS for Current-based Bearing Fault Diagnosis Ching-Che Chung, Hui-Hsuan Chang, and Ru-Tian Ko National Chung Cheng University
P1-39	Digital & System	Design and Implementation of a Hybrid Hardware Accelerator Architecture for Convolutional Neural Network and Large Language Model Chung-Bin Wu, Yi-Cheng Chen, Yu-Chen Hsu, Hu-Yi Tang, and Ying-Chieh Lin National Chung Hsing University
P1-40	Digital & System	Optimized Hardware Architecture and Implementation for Softmax Accelerator for LLMs Chung-Bin Wu, Chu-Hsuan Cheng, Yu-Chen Hsu, Hu-Yi Tang, and Ying-Chieh Lin National Chung Hsing University
P1-41	Digital & System	A Multimodal Geometric Conditional Generation Framework Integrating Text-to-Bounding Box and Text-to-Pose: Vector Integration and Image Generation Preliminary Study Bing-Ci Liu, Yu-Tung Hung, and Chun-Lung Hsu National Central University
P1-42	Digital & System	Subband-Aware and Dual-Branch Learning Algorithm for Ultra Lightweight ECG Denoising Autoencoder Design Shin-Chi Lai¹, Zheng-Rong Chen¹, Ying-Hsiu Hung¹, Yen-Ching Chang², Szu-Ting Wang³ ¹National Formosa University of Science and Technology, ²National Yunlin University of Science and Technology, ³Chaoyang University of Technology
P1-43	Digital & System	A Lightweight Compact Shortcut DAE with Simplified LSTM classifier Architecture for Edge ECG Denoising and Arrhythmia Recognition Shin-Chi Lai¹, Yen-Ching Chang², Ying-Hsiu Hung¹, Hui-Yu Liang², Kuan-Lin Liu², Zheng-Rong Chen¹, Ming-Hwa Sheu², and Shih-Chang Hsia² ¹National Formosa University ²National Yunlin University of Science and Technology
P1-44	Digital & System	Design and Verification of Built-In Self-Test Circuits for Passive-Quenching SPAD Arrays Yi-Jou Ho, Yi-Hsien Hung, and Pei-Cih Gao Feng Chia University
P1-45	Digital & System	Predictor Parameter Analysis and Hardware Architecture for CCSDS 123.0-B-2 Hyperspectral Image Compression Wei-Da Chen and Hung-Yu Tsai National Yunlin University of Science and Technology
P1-46	Digital & System	A Multi-Scale Dilated Convolutional Neural Network with Z-Score LMS for Edge-Based Wearable Heart Rate Estimation Shin-Chi Lai¹, Shang-Sian Wu¹, Szu-Ting Wang² ¹National Formosa University ²Chaoyang University of Technology
P1-47	EDA & Testing	High Accuracy Low Utilization Multi-Channel 2-ps Bin Size FPGA Digital-to-Time Converter Based on Compact Multi-Dimensional Delay Array Joshua Adiel Wijaya and Poki Chen National Taiwan University of Science and Technology
P1-48	EDA & Testing	Enhancing Machine Learning Resistance of Arbiter PUFs via FPGA-Aware Placement: A Study of Delay Correlation and Learnability Jun-Tsung Wu, Pei-Hsuan Lin, and Tong-Yu Hsieh National Sun Yat-sen University
P1-49	EDA & Testing	Stealthy Aging Trojans in Delay Locking Circuits via Path Delay Balancing Wen-Ti Tsai, Shu-Ching Yang, and Yu-Guang Chen National Central University
P1-50	EDA & Testing	Reliability Enhancement for 3D-DRAM by DQS Timing Calibration to Tolerate TSV Delay Variations Mao-Hsiang Lien, Wen-Chi Chen, and Shi-Yu Huang National Tsing Hua University
P1-51	EDA & Testing	Routing-Aware Simulated Annealing for Macro Placement Repair: Reopening SA with a Geometric Pre-Filter Chen-Hung Feng and Yao-Jen Chang Chung Yuan Christian University
P1-52	EDA & Testing	Phantom-Exit Congestion Optimization and Automatic QPO/SA Selection for an AI-Assisted Interactive Macro P&R Tool Yao-Jen Chang and Chen-Hung Feng Chung Yuan Christian University
P1-53	EDA & Testing	Study of GNN-Augmented Macro Placement Repair Compared to Geometric Pre-Filtering Chen-Hung Feng and Yao-Jen Chang Chung Yuan Christian University
P1-54	EDA & Testing	EM-Aware Placement for RF Analog Blocks on 28 nm 5G n78 Yao-Jen Chang, Chin-Chieh Hsu Chung Yuan Christian University
P1-55	EDA & Testing	Phantom-Exit Negotiated Routing and Layer-Stack-Aware Sign-Off for RF Analog Blocks on 28 nm 5G n78 Yao-Jen Chang, Chin-Chieh Hsu Chung Yuan Christian University
P1-56	Emerging Technologies	The CMOS Heavily Doped p+-Substrate with Negative Bias of Micromachined Magnetized Plasmonic Material Substrate on the Applications of the Plasmonic CMOS Bandgap Voltage Reference by Using the Technology of 0.18-µm CMOS Process in Theoretical Jiann-Long Wu^1,2, Yuh-Shyan Hwang¹, Huai-Kuei Wu² ¹National Taipei University of Technology ²Asia Eastern University of Science and Technology
P1-57	Emerging Technologies	The Polyphase Surface Processing Modification of Silicon Semiconductor Materials by Radio Frequency Produced Plasma at One Atmospheric Pressure Jiann-Long Wu^1,2, Yuh-Shyan Hwang¹, Huai-Kuei Wu² ¹National Taipei University of Technology ²Asia Eastern University of Science and Technology
P1-58	Emerging Technologies	A Q8.8 Fixed-Point VLSI Accelerator for Simulated Quantum Annealing with LUT-Based Nonlinear Function Units Ching-Jung Huang, Chi-Chia Sun National Taipei University
P1-59	Emerging Technologies	An Edge AI Driver Monitoring System Using DPU-Accelerated ResNet-18 on AMD KV260 I-An Lin, Yueh-Chun Lo, Sung-Yun Hsiao, Yu-Chuan Chen National United University
P1-60	Emerging Technologies	YOLOV4 Pruning with Learn Gates & BN and Channel Interdependence Learning Bo-Han Chen, Min-Xiang Chen, and Chia-Chi Tsai National Cheng Kung University

Poster 2

8月6日 (四) 10:50–12:00 鳳凰廳, 1F

場次主席

陳盈如, 國立成功大學

發表編號	類別	論文標題 / 作者 / 所屬學校/公司
P2-1	Analog & RF	Cost-Saving and High Efficiency DC Power Transmission Line with HFSS and ADS Tools on Energy-Saving Techniques Jiann-Long Wu^1,2, Yuh-Shyan Hwang¹, Huai-Kuei Wu² ¹National Taipei University of Technology ²Asia Eastern University of Science and Technology
P2-2	Analog & RF	Analysis And Research On A Dual-Mode Power Management Chip Applied To High-Speed Memory Wen-Shuo Chang, Shao-Ku Kao, Wan-Ju Li and Yu-Hsuan Lee Chang Gung University
P2-3	Analog & RF	The Applications of FIR Quasi-Digital Voltage Control Technique on the 0.18μm Embedded Buck Converter with Output Line-Dropped Compensation Ability, and Extremely Fast Stable Transient Response on EMI Effects Jiann-Long Wu^1,2, Yuh-Shyan Hwang¹, and Huai-Kuei Wu² ¹National Taipei University of Technology ²Asia Eastern University of Science and Technology
P2-4	Analog & RF	A Digital Buck Converter With Online Two-step Compensator Auto-tuning Mechanism Yu-Jen Chen, Chia-Hao Chang, and Chien-Hung Tsai National Cheng Kung University
P2-5	Analog & RF	A Three-Stage Adaptive Gate Driver with Gate Sensing for SiC Power Device Turn-ON Optimization Yu-Kai Wang and Pang-Jung Liu National Taipei University of Technology
P2-6	Analog & RF	A High-Efficiency Buck Converter Supporting Large Dynamic Loads for AIoT Applications Po-Chuan Wang¹, Yuh-Shyan Hwang¹, and Dong-Shiuh Wu² ¹National Taipei University of Technology ²Lunghwa Univ. of Science and Technology
P2-7	Analog & RF	A Current-Mode Buck Converter with Transient Acceleration Circuit and Low-IQ Comparator Luo-Yen Chuang¹, Yuh-Shyan Hwang², and Dong-Shiuh Wu³ ¹National Taipei University of Technology ²National Taipei University of Technology ³Lunghwa Univ. of Science and Technology
P2-8	Analog & RF	A Buck Converter with Capacitor Current Inverse-Charge Constant On-Time Control Hung-Ta Chen¹, Yuh-Shyan Hwang¹, and Dong-Shiuh Wu² ¹National Taipei University of Technology ²Lunghwa Univ. of Science and Technology
P2-9	Analog & RF	An Adaptive On-Time Controlled Buck Converter with Load-Sensing Technique Achieving DCM Constant Output Ripple Wen-Shih Tseng¹, Yuh-Shyan Hwang¹, and Dong-Shiuh Wu² ¹National Taipei University of Technology ²Lunghwa Univ. of Science and Technology
P2-10	Analog & RF	A Constant-On-Time Controlled Buck Converter with Integrated Protection and Zero-Current Detection Wen-Hsiu Hu¹, Yuh-Shyan Hwang¹, and Dong-Shiuh Wu² ¹National Taipei University of Technology ²Lunghwa Univ. of Science and Technology
P2-11	Analog & RF	Design and Implementation of High-Speed Avalanche Photodiode Measurement System Based on High-Voltage BCD Technology Jheng-Jyun Lian, Chorng-Jiun Chen, and Po-Yu Kuo National Yunlin University of Science & Technology
P2-12	Analog & RF	Half-Rate Reference-less Clock and Data Recovery for Optical Receivers in 65-nm CMOS Meng-Ling Chiang, Jenny Yi-Chun Liu, and Chia-Hao Chuang National Tsing Hua University
P2-13	Analog & RF	Design of a High-Performance Millimeter-Wave Receiver Front-End for 5G Communications Pei-Ci Chuang and Jenny Yi-Chun Liu National Tsing Hua University
P2-14	Analog & RF	5GHz Phase-Locked Loop with Power-Improved Charge Pump Sheng-Chun Chuang, Hung-Wei Chai, and Ko-Chi Kuo National Sun Yat-sen University
P2-15	Analog & RF	RF-ESD Co-Design of a High-Speed TIA and Bypass Circuit for Optical Receiver Front-Ends Er-Wen Chien, Cheng-Han Chiang and Chun-Yu Lin National Yang Ming Chiao Tung University
P2-16	Analog & RF	A 20-Gb/s Continuous-Time Linear Equalizer with Feedforward Frequency Compensation in 40-nm CMOS Hung-Wen Lin, Yi-Tso Chang, Yue-Chi Hung, and Kai-Xiang Zhang Yuan Ze University
P2-17	Analog & RF	Design of 2-turn 8-Shaped Inductors Used in VCO Sheng–Lyang Jang¹, Bo-Rui Dai², and Wen-Cheng Lai² ¹Ming Chi University of Technology ²National Taiwan University of Science and Technology
P2-18	Analog & RF	A Low-Power Harmonic-Resilient Mixer-First Receiver Using Third-Harmonic N-Path Mixing Jhih-Hao Hong, Tang-Ruei-Cheng Chen and Kuang-Wei Cheng National Cheng Kung University
P2-19	Analog & RF	An SSC Tracking Aid for Dual-Loop Digital CDRs Tse-Hsuan Chen and Ping-Hsuan Hsieh National Tsing Hua University
P2-20	Digital & System	Fully-Digital, ROM-less Sine and Gaussian Wave Generator with Linear Approximation and Error Correction Joshua Adiel Wijaya and Poki Chen National Taiwan University of Science and Technology
P2-21	Digital & System	Hardware-Aware Image Resampling for FPGA-Based UAV Localization with Parameter-Guided ORB Matching Jing-Yuan Ye and Hsi-Pin Ma National Tsing Hua University
P2-22	Digital & System	Low-Power Approximate Computing Circuit Design for Fast Image Processing Deng-Yao Yao, Jian-Fu Tsai, and Kun-Lin Tsai Tunghai University
P2-23	Digital & System	A Region-Based Hop-to-Hop Topological Validation for Securing NoC Multicast Dai-Ling (Hannah) Chen and Kun-Chih (Jimmy) Chen National Yang Ming Chiao Tung University
P2-24	Digital & System	A Compression-Aware Event Transformer Accelerator with Sparse Feature Transfer for Airborne Edge Perception Tzu-Heng Lin and Pei-Jun Lee National Taiwan University of Science and Technology
P2-25	Digital & System	Adaptive Tensor Compression and Memory Offloading for Reliable and Efficient LLM Training Chia-Tung Hsieh, Chin-Hsien Wu, and Meng-Che Chao National Taiwan University of Science and Technology
P2-26	Digital & System	Design Space Exploration of a BRAM-Less Sobel Accelerator on Resource-Constrained FPGAs Using HLS I-An Lin, Yan-Jhih Jhang, Tian-Feng Wang, and Wei-Tsen Lin National United University
P2-27	Digital & System	A Group-Wise Sign-Remapped Partial-Product Scheme for SRAM-DCIM MACs Meng-Hsun Yang¹, Yu-Hsien Lin¹, Katherine Shu-Min Li¹, Chun-Lung Hsu² ¹National Sun Yat-sen University ²National Central University
P2-28	Digital & System	Stride–NMS Co-Design for Vision Transformer Hotspot Detection: A Diagnostic Study on the Precision Bottleneck Cheng-Wei Chang and Yao-Jen Chang Chung Yuan Christian University
P2-29	Digital & System	A Heterogeneous System for Event-Based Video Reconstruction Using Hybrid-EVSNN Chih-Cheng Chen, Yu-Hsiang Chiu, Cheng-Ru Kuan and Chun-Lung Hsu National Central University
P2-30	Digital & System	Design and FPGA Implementation of an Ultra-lightweight Ternary-Weight YOLO Inference Processor Huai-Chieh Hsieh and Tzi-Dar Chiueh National Taiwan University
P2-31	Digital & System	Layer-wise Mixed-Precision Quantization with HLS Pragma Co-Optimization for Resource-Constrained FPGAs: A Case Study on PYNQ-Z2 Kiat Siong Ng National Yunlin University
P2-32	Digital & System	Design and Implementation of a Low-Bit Inference Acceleration Processor for Large Language Models Based on Transformers and State-Space Models Ting-Yi Wu and Tzi-Dar Chiueh National Taiwan University
P2-33	Digital & System	Unsupervised Reinforcement STDP Learning Methodology via Spike-based Intrinsic Reward Wen-Shuo Cheng and Kun-Chih Chen National Yang Ming Chiao Tung University
P2-34	Digital & System	Real-Time Medical Waste Classification Using Convolutional Neural Networks with Hardware Acceleration Yi-Hung Lin, Zhao-Xin Pan, I-Ting Wu, and Yu-Guang Chen National Central University
P2-35	Digital & System	Permutation-State Sparse-Delta Annealing for CIM-Compatible TSP Acceleration Kuan-Chung Chen and Sheuan-Chang Tian National Yang Ming Chiao Tung University
P2-36	Digital & System	FPGA-Based Acceleration of Vision Transformers with Quantization and Token Reduction Cheng-Wei Yu, Edwin Arkel Rios, Yu-Jung Hsu, Ling-Chi Yang, Cheng-Ching Lin, and Bo-Cheng Lai National Yang Ming Chiao Tung University
P2-37	Digital & System	A 32x8 bits Fast-Access Static Random Access Memory Array Circuit with Dual-Output Functionality Wei-Hsiang Huang, Liang-Chi Huang, Bo-Hsun Juan, Pen-Yi Chu and Tzu-Hsuan Chang National Taiwan University
P2-38	Digital & System	A Study of Lightweight CNN and Model Compression for Wafer Defect Classification on Resource-Constrained FPGA CHENG-YI YANG, JHONG-BI WEI National Changhua University of Education
P2-39	Digital & System	Design and Implementation of an Offline Infant Safety Monitoring System for Outdoor Scenarios Rong-Wan Yang, You-Zhen Lin, Yu-Jun Hsiao, Ting-Chen Lin, and Yu-Guang Chen National Central University
P2-40	Digital & System	Smooth Exponent Optimization for Hardware-Friendly Post-Training Quantization Yu-Ting Shi, Yung-Sheng Lin, Bo-Han Chen, and Chia-Chi Tsai National Cheng Kung University
P2-41	Digital & System	An Efficient Hardware Architecture for Rotary Position Embedding with Extensible Variant Support Shao-Qi Lee and Yun-Nan Chang National Sun Yat-sen University
P2-42	EDA & Testing	A Test Data Compression Technique Using Geometric Shape Mapping Andre Chan¹, Wang-Dauh Tseng² ¹Amador Valley High School ²Yuan Ze University
P2-43	EDA & Testing	High-Performance APB Transaction Error Detection via Efficient VCD Waveform Processing Ting Yi Wang, Shang Yuan Wu, Ming Sheng Yang, Bo Sen Chang, and Yu Guang Chen National Central University
P2-44	EDA & Testing	A Data-Driven Hybrid Bucketing Framework for Automated RTL Regression Failure Triage Ciao-Ying Su, Po-Hao Chen, Fa-Hong Liu, Ting-Ying Chien, and Yu-Cheng Lin Yuan Ze University
P2-45	EDA & Testing	Residual-Driven Adaptive Test Pattern Generation Yen-Hao Chen and Jiann-Chyi Rau Tamkang University
P2-46	EDA & Testing	SAEG-LinUCB: A Contextual-Bandit Framework for Hierarchical ATPG Strategy and Hardware Scheduling Xuan-Wen Qiu and Jiann-Chyi Rau Tamkang University
P2-47	EDA & Testing	Learning-Based Temperature Scheduling for Simulated Annealing in VLSI CAD Wang Yi-Shiang and Kun-Chih Chen National Yang Ming Chiao Tung University
P2-48	EDA & Testing	A Single-Port SRAM Compiler for ASAP7 PDK Shao-Chien Lu, Yi-Chia Wu, Yu-Cheng Lin, and Rung-Bin Lin Yuan Ze University
P2-49	EDA & Testing	LSAU-Net: A Layer-Scalable Attention U-Net for Fast Steady-State Thermal Prediction in 3D ICs Ying-Hui Lin and Yu-Min Lee National Yang Ming Chiao Tung University
P2-50	EDA & Testing	Efficient Thermal Simulation for 3D-Stacked ICs Considering Lateral Heat Spreading and Structural Heterogeneity Hung-Yang Chen, Ching-Hsiang Wang, Zhu-You Lu, and Yu-Min Lee National Yang Ming Chiao Tung University
P2-51	EDA & Testing	Viability of LLM-Based Soft Block Floorplanning Ping-Li Tien, Guan-Ting Lu, Yung-An Chen, Yu-Cheng Lin, and Rung-Bin Lin Yuan Ze University
P2-52	EDA & Testing	PG-GNN: Physics-Guided Graph Neural Network for Fast and Accurate Cell Timing Library Characterization Jason W.-Y. Cheng, Gordon K.-D. Hsu, Jeffery Y.-C. Chen, Aaron C.-W. Liang, and Charles H.-P. Wen National Yang Ming Chiao Tung University
P2-53	EDA & Testing	SPICE Model for ESD Protection Capability of 1200 V SiC MOSFET Po-Yu Cheng¹, Ruei-Ci Wu², Pei-Chi Liao¹, Kung-Yen Lee¹, Wei-Xiang Wang¹, Yan-Yu Wen¹, Tie Chin Shih¹, and Chih-Yen Teng¹ ¹National Taiwan University ²SiCEV Electronics Co., Ltd
P2-54	EDA & Testing	ThTrace: A High-Efficiency Displacement Field Simulator for Advanced Packaging Yong-Han Lin, Pei-Yu Huang, Jen-Yi Wang, and Yu-Min Lee National Yang Ming Chiao Tung University
P2-55	EDA & Testing	OPC+: GPU-Accelerated Lithography Simulation with Contour-Based Calibration and Unified Inverse Mask Optimization Po-Hsun Fang, Pokai Chang, Kuan-Hsun Wang, Zhi-Sheng Wang, Han-Xuan Huang, Shie-Yuan Wang, and Peichen Yu National Yang Ming Chiao Tung University
P2-56	EDA & Testing	An Application-Oriented Design Space Exploration Framework for Digital Compute-in-Memory Systems Po-Yuan Kuo, Chung-Yu Wang, Jyun-Bin Kuo, Ching-Hsiu Lin, and Chun-Lung Hsu National Central University
P2-57	EDA & Testing	Stage-Aware Layout–Mask–Contour Modeling for Learning-Based Lithography Prediction Zih-Min Huang, Da-Jhong Chen, Te-An Chien, Yu-Cheng Chen, and Hao-Chiang Shao National Chung Hsing University
P2-58	EDA & Testing	SPICE Model for Dynamic Electro-Thermal Modeling and Short-Circuit Failure Analysis of 650V SiC MOSFETs Chun-Wei Yeh, Kung-Yen Lee, Po-Yu Cheng, Yi-Pin Lee, Jui-Chi Chu, Jung-Chieh Chen, and Yu-Ying Li National Taiwan University
P2-59	EDA & Testing	A Robust LLM-Assisted System for Gate-Level Netlist Analysis and Transformation Hao-En Chu, Tsung-Yu Chang, Yung-An Chen, and Yu-Cheng Lin Yuan Ze University