TSRI Special Session & Short Course

TSRI Special Session schedule — August 4, 2026 — 水景廳, 3F
8/4(二) TSRI Special Session (水景廳, 3F)
14:30–15:30 報到
15:00–15:10 開場 劉建男主任
15:10–15:50 年度優良晶片頒獎
15:50–16:05 TSRI 重大策略說明 劉建男主任
16:05–16:25 TSRI 晶片服務業務說明 蔡瀚輝副主任
16:25–17:00 Q&A
17:00–17:20 抽大獎
TSRI Short Course schedule — August 4, 2026 — 水景廳, 3F
8/4(二) TSRI Short Course (水景廳, 3F)
19:00–19:50
19:50–20:00 抽大獎 + 換場休息時間 5min
20:00–20:40
20:40–20:45 抽大獎

Short Course Details / 課程與講者

陳克明
TSRI Short Course (1)

Scale Academic FinFET IC Design with TSMC University FinFET Program 2.0

陳克明
TSMC / 副處長
August 4, 2026 (Tuesday) 19:00–19:50 水景廳, 3F
Biography / 個人簡介

Clark Chen is Deputy Director of TSMC University Program under Corporate Research. He has served TSMC over 29 years in multiple positions including IC design and design ecosystem enablement. He holds 33 US patents and is one of the initiators of TSMC University FinFET Program.

李元璞
TSRI Short Course (2)

AI-Driven Analog IC Design Using ASO.ai

李元璞
TSRI Chip Implementation Service Division / Associate Engineer
August 4, 2026 (Tuesday) 19:00–19:50 水景廳, 3F
Biography / 個人簡介

Mr. Lee holds a Master's degree in Electronics Engineering from National Tsing Hua University. He has over 15 years of experience in analog IC design across several design houses, along with 5 years of experience in EDA tool verification at an EDA company. This unique combination of expertise enables him to bridge the gap between analog circuit design and design automation.

Currently, he focuses on promoting the practical application of AI-driven optimization (ASO.ai) in analog IC design. In addition, he serves as an instructor for ASO.ai training courses at TSRI, helping engineers leverage AI technologies to enhance design productivity and innovation.

蕭仲容
TSRI Short Course (3)

A.I.-Driven RTL-to-GDS Design Optimization Tutorial

蕭仲容
SiCADA / 協理
August 4, 2026 (Tuesday) 20:00–20:40 水景廳, 3F
Biography / 個人簡介

Mr. Chung-Jung Hsiao (AKA Charles Hsiao) currently serves as Director at SiCADA. He previously worked as a Senior Technical Engineer at Synopsys, specializing in Fusion Compiler and IC Compiler II applications. He has also held senior engineering and application engineering roles at leading global companies, including Texas Instruments, IBM, and LSI Logic, with extensive experience spanning the entire IC design process from floorplanning to final tape-out.

With over 30 years of experience in the IC design industry, his technical expertise includes advanced process node design flow validation, IC physical design (including floorplanning, optimization, clock tree synthesis, power planning, and routing), as well as physical design project management and customer-facing technical support. He is recognized for his strong cross-functional communication skills and international project experience.

Charles Hsiao holds a Master’s degree in Electrical Engineering from San Jose State University and has dedicated to IC design technology applications and talent development.